Sunday, January 18, 2009

Instantiating Block RAM for Spartan 3E in VHDL without using COREGEN

Screw Coregen!

To use block RAMs directly, use RAMB primitives given in the Xilinx primitives handbook (here: http://www.xilinx.com/itp/xilinx9/books/docs/s3edl/s3edl.pdf.

The question not answered is how to insert them into the VHDL. Obviously they need to be called out as a component somehow.

The answer was in Xilinx's block ram application note (http://www.xilinx.com/support/documentation/application_notes/xapp463.pdf) but did not jump out on initial reading. It took this forum thread to point out that there are quite easy to use templates for intantiating primitives built right into ISE. In ISE, Edit => Language Templates => VHDL => Component Instantiation => Block RAM (it gets a little more complicated than that at the end, but the basic idea is there). This gives the component declaration, and most importantly the library call that contains the actual primitive, both as a bitmap and as a simulation library.

Most of the forum threads out there on this subject are entirely devoted to how to use the INIT label or whatever to specify the initial contents of the RAM. Not sure why this is so worried over.

Also, the Spartan3e RAM primitive declaration has a fancy "SSR" line which is separate from the gbinit; gbinit produces the contents specified in the INITs, SSR is some weird enable for putting a constant output on the data lines regardless of the value of the address lines.

Tuesday, January 6, 2009

5V to 3.3V signal translation

Results of recent search for available translation technologies:

1. CD4050 hex buffer can run from 3V to 18V but accepts higher than VDD level on the inputs. However, at 5V requires at least 3.5V for high level inputs. datasheet here

2. SN74LVCC3245A is the dual supply transciever commonly in use here. Comes in surface mount only. A side must be between 2.3 to 3.6V, B side must be between 3V to 5.5V. Control lines are on the A side. datasheet here

3. SN74LVC4245A is another dual supply transciever using LVC-only technology. Very similar to 74LVCC3245A except that on this one the A side is locked to 5V and the B side is 3.3V. DIR and OE are on side A. datasheet here

4. It turns out that there's a SN74LVCC4245A, which has the A port being the 5V side, but the range on the B port goes from 2.7V to 5.5V. This might be the one that I thought I was using when building the breadboard. datasheet here

5. The SN74LVC245A runs at 1.65V to 3.6V but can handle input levels up to 5.5V. datasheet here

6. Similarly, the SN74LVC244 runs at low voltages and can handle 5V inputs.

7. The 74HCT244, if run at 5V, requires only 2V as an input high level (consistent with TTL characteristics). datasheet here

8. The CD40109 is a low-to-high translator, but is only 4 to a package.

9. The CD4504 is also available in DIP, is a hex buffer that accepts extremely high input voltages above it's VDD, but it's not clear if it can be run at 3.3V

10. here's a fascinating forum thread where a bunch of other ideas, including the CD4504 are discussed.