Fun test equipment

Just some links to different types of fun and expensive lab equipment that I had to look up the price for during inventory.

Rohde & Schwarz SMA100A RF Signal Generator: https://www.testequity.com/products/1478/

The Total Verification System: https://ingenionllc.sharepoint.com/Pages/Products.aspx

34470A Digital Multimeter, 7½ Digit, Performance Truevolt DMM: http://www.keysight.com/en/pd-2520154-pn-34470A/digital-multimeter-7-digit-performance-truevolt-dmm?cc=US&lc=eng

Agilent 34420A Nanovolt / Micro‑Ohm Meter: http://www.keysight.com/en/pd-1000001296%3Aepsg%3Apro-pn-34420A/micro-ohm-meter?cc=US&lc=eng

SMA Cables: https://www.digikey.com/products/en?keywords=415-0029-036

Teledyne LeCroy PCIe Protocol Analyzer: http://teledynelecroy.com/protocolanalyzer/protocoloverview.aspx?seriesid=467

Interposer for Teledyne LeCroy Protocol Analyzer: http://teledynelecroy.com/protocolanalyzer/protocoloverview.aspx?seriesid=118&capid=103&mid=511

All the protocol analyzers: http://teledynelecroy.com/shopper/requestquote/configure_small_step1.aspx?catid=19

Protocol Analyzer overview: http://cdn.teledynelecroy.com/files/pdf/pcie_interposer_datasheet.pdf

Datasheet for the Gen2 x8 interposer: http://psirep.com/sites/default/files/gen2_x8_active_interposer.pdf

Here is the 1982-era spectrum analyzer that Nga is using: http://www.thinksrs.com/products/SR760770.htm

Holy Crap, Rhode & Scharz makes an oscilloscope! I think it's made of solid gold. They also have a handheld scope that is like something from the next decade: https://www.rohde-schwarz.com/us/products/test-measurement/oscilloscopes/pg_overview_63663.html

Here are a couple of links to the fun-looking but ultimately useless Zed Board that we attempted to do some VHDL development on:

Here's the overview: https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html#overview

Here's the datasheet: http://zedboard.org/sites/default/files/documentations/ZedBoard_HW_UG_v2_2.pdf

Here's a search for ideas on how to get the LVDS lines out of the FMC connector: https://www.google.com/search?q=FMC+LPC+to+LVDS

step-by-step using COREGEN

To include a fifo from COREGEN in the design, do this:

1. Insert the component and port map from the .vho file in your VHDL at the appropriate places.

2. Add the EDN file as the source for the component

3. Make sure the ngc file is in the same directory as the project or it just won't fucking compile. Adding the ngc as a source file doesn't work. Actually, to be safe, just either generate the core into the project directory rather than a subdirectory, or copy all the files up from the subdirectory.

3a. This link has a clue (in answer #4) on how to add the subdirectory to the search path, but I'm not sure that it's worth the trouble, and the clue is not complete:

http://thedailyreviewer.com/hardware/view/xilinx-ise-constanly-asking-to-regenerate-a-core-file-111129027

Bit by Xilinx again - FSM in BRAM

First attempt to move my FSMs into BRAM failed with this message:

"ERROR: Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict..."

Most of the xilinx forum posts on this problem are answered with "we don't know, have you tried more RAM?". Some interesting other responses:

This is the most pertinent response, which talks about a few cases which produce this problem. It hints that piecemeal compilation is possible but I've never seen hints of how to do this before:

http://www.xilinx.com/support/answers/15336.htm

This guy seems to know what he's talking about, and he heroically bought a new computer, then switched to Linux to get it to work:
http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=4524

This guy also went to heroic lengths, and came to the conclusion that he was being limited solely by computing power, wants supercomputers in The Cloud to do it for him.
http://fpgacomputing.blogspot.com/2009_07_01_archive.html

This hint was for possibly an older version of XST, but it offers the hope (taken) that I can just turn off RTL Schematic generation:
http://www.xilinx.com/support/answers/16904.htm

How to get ISE 8.2i from Xilinx

Old versions of WebPACK can still be downloaded from here:

http://www.xilinx.com/ise/logic_design_prod/classics.htm

Instantiating Block RAM for Spartan 3E in VHDL without using COREGEN

Screw Coregen!

To use block RAMs directly, use RAMB primitives given in the Xilinx primitives handbook (here: http://www.xilinx.com/itp/xilinx9/books/docs/s3edl/s3edl.pdf.

The question not answered is how to insert them into the VHDL. Obviously they need to be called out as a component somehow.

The answer was in Xilinx's block ram application note (http://www.xilinx.com/support/documentation/application_notes/xapp463.pdf) but did not jump out on initial reading. It took this forum thread to point out that there are quite easy to use templates for intantiating primitives built right into ISE. In ISE, Edit => Language Templates => VHDL => Component Instantiation => Block RAM (it gets a little more complicated than that at the end, but the basic idea is there). This gives the component declaration, and most importantly the library call that contains the actual primitive, both as a bitmap and as a simulation library.

Most of the forum threads out there on this subject are entirely devoted to how to use the INIT label or whatever to specify the initial contents of the RAM. Not sure why this is so worried over.

Also, the Spartan3e RAM primitive declaration has a fancy "SSR" line which is separate from the gbinit; gbinit produces the contents specified in the INITs, SSR is some weird enable for putting a constant output on the data lines regardless of the value of the address lines.