Sequencer work

Misc links to remember for future steps of compiling my sequencer demo:

The page which answered the question about whether processes in testbenches are repeating:

http://www.embeddedrelated.com/showarticle/31.php

The page which showed that the fuction conv_to_std_logic_vector seemed to demand a variable rather than an integer or other signal:

http://www.quest4tech.net/hardware/vhdl/techniques/

And some info about variables in VHDL:

http://www.gmvhdl.com/variable.htm

An illustrative public debate about the hazards of using asynchronous signals for a state machine.

http://www.fpgarelated.com/usenet/fpga/show/94294-1.php

The Actel PDF about the EDAC RAM:

http://www.actel.com/documents/EDAC_71_AN.pdf

The first hit on my search for information about the Actel RAM4K9 primitive used by Waltero and others:

http://www.kxcad.net/actel_designer/actel_designer_online_help/ACTgenIII%20files/a3_ProASIC3E_RAM4k9.htm

Bit by Xilinx again - FSM in BRAM

First attempt to move my FSMs into BRAM failed with this message:

"ERROR: Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict..."

Most of the xilinx forum posts on this problem are answered with "we don't know, have you tried more RAM?". Some interesting other responses:

This is the most pertinent response, which talks about a few cases which produce this problem. It hints that piecemeal compilation is possible but I've never seen hints of how to do this before:

http://www.xilinx.com/support/answers/15336.htm

This guy seems to know what he's talking about, and he heroically bought a new computer, then switched to Linux to get it to work:
http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=4524

This guy also went to heroic lengths, and came to the conclusion that he was being limited solely by computing power, wants supercomputers in The Cloud to do it for him.
http://fpgacomputing.blogspot.com/2009_07_01_archive.html

This hint was for possibly an older version of XST, but it offers the hope (taken) that I can just turn off RTL Schematic generation:
http://www.xilinx.com/support/answers/16904.htm

Instantiating Block RAM for Spartan 3E in VHDL without using COREGEN

Screw Coregen!

To use block RAMs directly, use RAMB primitives given in the Xilinx primitives handbook (here: http://www.xilinx.com/itp/xilinx9/books/docs/s3edl/s3edl.pdf.

The question not answered is how to insert them into the VHDL. Obviously they need to be called out as a component somehow.

The answer was in Xilinx's block ram application note (http://www.xilinx.com/support/documentation/application_notes/xapp463.pdf) but did not jump out on initial reading. It took this forum thread to point out that there are quite easy to use templates for intantiating primitives built right into ISE. In ISE, Edit => Language Templates => VHDL => Component Instantiation => Block RAM (it gets a little more complicated than that at the end, but the basic idea is there). This gives the component declaration, and most importantly the library call that contains the actual primitive, both as a bitmap and as a simulation library.

Most of the forum threads out there on this subject are entirely devoted to how to use the INIT label or whatever to specify the initial contents of the RAM. Not sure why this is so worried over.

Also, the Spartan3e RAM primitive declaration has a fancy "SSR" line which is separate from the gbinit; gbinit produces the contents specified in the INITs, SSR is some weird enable for putting a constant output on the data lines regardless of the value of the address lines.