Screw Coregen!
To use block RAMs directly, use RAMB primitives given in the Xilinx primitives handbook (here: http://www.xilinx.com/itp/xilinx9/books/docs/s3edl/s3edl.pdf.
The question not answered is how to insert them into the VHDL. Obviously they need to be called out as a component somehow.
The answer was in Xilinx's block ram application note (http://www.xilinx.com/support/documentation/application_notes/xapp463.pdf) but did not jump out on initial reading. It took this forum thread to point out that there are quite easy to use templates for intantiating primitives built right into ISE. In ISE, Edit => Language Templates => VHDL => Component Instantiation => Block RAM (it gets a little more complicated than that at the end, but the basic idea is there). This gives the component declaration, and most importantly the library call that contains the actual primitive, both as a bitmap and as a simulation library.
Most of the forum threads out there on this subject are entirely devoted to how to use the INIT label or whatever to specify the initial contents of the RAM. Not sure why this is so worried over.
Also, the Spartan3e RAM primitive declaration has a fancy "SSR" line which is separate from the gbinit; gbinit produces the contents specified in the INITs, SSR is some weird enable for putting a constant output on the data lines regardless of the value of the address lines.
