Two nice versions of the same idea for making a divider in VHDL without doing stupid loops:
Here it is in simple, non-machine code:
http://www.missiontech.co.nz/index.php?page=read-an-article&articleId=85
Here is the same idea, implemented fully using cascades of adders/subtracters
http://www.cs.umbc.edu/portal/help/VHDL/samples/samples.shtml
And, surprisingly, here's all the source code for the above so that you don't have to do any thinking yourself:
http://www.cs.umbc.edu/~squire/download/divcas4_test.vhdl
