For an FPGA, getting specific frequencies from the system clock involves things like "divide by 5". This turns out to be a little tricky if you want a real clock output with something resembling a 50% duty cycle. Some answers that I recently stumbled on include.
1. Use a PLL module if the FPGA has them, since they have multipliers and dividers built in that can make multiples or fractions of the input clock.
2. Use two binary dividers and combine them in novel ways that I don't completely understand yet. However, the following papers seem to explain it:
A SNUG paper from 2002 by ST Microelectronics, the original of which seems to not have the text contained in the still-barely-readable google cache:
http://74.125.95.132/search?q=cache:XH_x-8eBw-4J:www.scribd.com/doc/6868408/Clock-Dividers+vhdl+%22divide+by+5%22+counter+example&cd=6&hl=en&ct=clnk&gl=us
(original, seems to be working now: http://www.scribd.com/doc/6868408/Clock-Dividers)
Here seems to be some examples similar to the above, except the code makes no sense to me (particularly if x=n then x=x+1):
http://www.asic-world.com/examples/vhdl/counters.html
The first question in this quiz with answers looks interesting, but the problem in the outputs is not entirely clear:
http://www.ece.stevens-tech.edu/~bmcnair/SwTh-Sum04/quiz4-with-answers.pdf
