To include a fifo from COREGEN in the design, do this:
1. Insert the component and port map from the .vho file in your VHDL at the appropriate places.
2. Add the EDN file as the source for the component
3. Make sure the ngc file is in the same directory as the project or it just won't fucking compile. Adding the ngc as a source file doesn't work. Actually, to be safe, just either generate the core into the project directory rather than a subdirectory, or copy all the files up from the subdirectory.
3a. This link has a clue (in answer #4) on how to add the subdirectory to the search path, but I'm not sure that it's worth the trouble, and the clue is not complete:
http://thedailyreviewer.com/hardware/view/xilinx-ise-constanly-asking-to-regenerate-a-core-file-111129027
