Misc links to remember for future steps of compiling my sequencer demo:
The page which answered the question about whether processes in testbenches are repeating:
http://www.embeddedrelated.com/showarticle/31.php
The page which showed that the fuction conv_to_std_logic_vector seemed to demand a variable rather than an integer or other signal:
http://www.quest4tech.net/hardware/vhdl/techniques/
And some info about variables in VHDL:
http://www.gmvhdl.com/variable.htm
An illustrative public debate about the hazards of using asynchronous signals for a state machine.
http://www.fpgarelated.com/usenet/fpga/show/94294-1.php
The Actel PDF about the EDAC RAM:
http://www.actel.com/documents/EDAC_71_AN.pdf
The first hit on my search for information about the Actel RAM4K9 primitive used by Waltero and others:
http://www.kxcad.net/actel_designer/actel_designer_online_help/ACTgenIII%20files/a3_ProASIC3E_RAM4k9.htm
